An Architectural Approach for Decoding and Distributing Functions in FPUs in a Functional Processor System

TL;DR

This paper proposes an architectural approach for decoding and distributing functions across FPUs in a functional processor system, focusing on function segregation and address mapping to enhance processing efficiency.

Contribution

It introduces a novel method for decoding function pipelines and distributing them to FPUs, advancing the design of functional processor systems.

Findings

Explored function segregation from application programs.

Proposed address mapping techniques for function distribution.

Theoretical framework for functional processor architecture.

Abstract

The main goal of this research is to develop the concepts of a revolutionary processor system called Functional Processor System. The fairly novel work carried out in this proposal concentrates on decoding of function pipelines and distributing it in FPUs as a part of scheduling approach. As the functional programs are super-level programs that entails requirements only at functional level, decoding of functions and distribution of functions in the heterogeneous functional processor units are a challenge. We explored the possibilities of segregation of the functions from the application program and distributing the functions on the relevant FPUs by using address mapping techniques. Here we pursue the perception of feeding the functions into the processor farm rather than the processor fetching the instructions or functions and executing it. This work is carried out at theoretical levels and it requires a long way to go in the realization of this work in hardware perhaps with a large industrial team with a pragmatic time frame.