Minor-embedding in adiabatic quantum computation: II. Minor-universal graph design

TL;DR

This paper explores the design of hardware graphs for adiabatic quantum computing that can efficiently embed a wide range of problem graphs, focusing on minor-universal graphs and their properties.

Contribution

It introduces the concept of F-minor-universal hardware graphs and discusses the challenges in designing such graphs for sparse graph families.

Findings

Presented an optimal complete-graph-minor hardware graph

Defined the concept of F-minor-universal graphs for quantum hardware

Highlighted open problems in designing sparse minor-universal hardware graphs

Abstract

In [Choi08], we introduced the notion of minor-embedding in adiabatic quantum optimization. A minor-embedding of a graph G in a quantum hardware graph U is a subgraph of U such that G can be obtained from it by contracting edges. In this paper, we describe the intertwined adiabatic quantum architecture design problem, which is to construct a hardware graph U that satisfies all known physical constraints and, at the same time, permits an efficient minor-embedding algorithm. We illustrate an optimal complete-graph-minor hardware graph. Given a family F of graphs, a (host) graph U is called F-minor-universal if for each graph G in F, U contains a minor-embedding of G. The problem for designing a F-minor-universal hardware graph U_{sparse} in which F consists of a family of sparse graphs (e.g., bounded degree graphs) is open.