Classifying Application Phases in Asymmetric Chip Multiprocessors

TL;DR

This paper investigates program execution phase detection in asymmetric chip multiprocessors to enhance performance and reduce power, using dynamic profiling intervals that significantly lower profiling overhead.

Contribution

It introduces a dynamic profiling interval adjustment algorithm for phase detection in heterogeneous multicore processors, reducing overhead and improving phase classification accuracy.

Findings

Dynamic profiling reduces overhead by over three times.

Phase classification based on throughput and utilization is effective.

Results demonstrate improved performance in multiprocessor benchmarks.

Abstract

In present study, in order to improve the performance and reduce the amount of power which is dissipated in heterogeneous multicore processors, the ability of detecting the program execution phases is investigated. The programs execution intervals have been classified in different phases based on their throughput and the utilization of the cores. The results of implementing the phase detection technique are investigated on a single core processor and also on a multicore processor. To minimize the profiling overhead, an algorithm for the dynamic adjustment of the profiling intervals is presented. It is based on the behavior of the program and reduces the profiling overhead more than three fold. The results are obtained from executing multiprocessor benchmarks on a given processor. In order to show the program phases clearly, throughput and utilization of execution intervals are presented on a scatter plot. The results are presented for both fixed and variable intervals.