Design and Analysis of a Spurious Switching Suppression Technique Equipped Low Power Multiplier with Hybrid Encoding Scheme

TL;DR

This paper introduces a low power multiplier design with a hybrid encoding scheme that significantly reduces switching activity and power consumption in digital signal processing applications.

Contribution

It proposes a novel encoding technique combined with a low power adder architecture to minimize switching activity and power consumption in multipliers.

Findings

Switching activity reduced by 86% compared to conventional multipliers.

Power consumption decreased by 87% relative to conventional designs.

The approach is validated through device-level simulation results.

Abstract

Multiplication is an arithmetic operation that is mostly used in Digital Signal Processing (DSP) and communication applications. Efficient implementation of the multipliers is required in many applications. The design and analysis of Spurious Switching Suppression Technique (SSST) equipped low power multiplier with hybrid encoding is presented in this paper. The proposed encoding technique reduces the number of switching activity and dynamic power consumption by analyzing the bit patterns in the input data. In this proposed encoding scheme, the operation is executed depends upon the number of 1s and its position in the multiplier data. The architecture of the proposed multiplier is designed using a low power full adder which consumes less power than the other adder architectures. The switching activity of the proposed multiplier has been reduced by 86 percent and 46percent compared with conventional and Booth multiplier respectively. It is observed from the device level simulation using TANNER 12.6 EDA that the power consumption of the proposed multiplier has been reduced by 87 percent and 26 percent compared with conventional and Booth multiplier.