Solid-state memcapacitive system with negative and diverging capacitance

TL;DR

This paper proposes a solid-state memcapacitive system using a multi-layer structure with tunneling, exhibiting hysteresis, negative, and diverging capacitance, enabling potential information storage applications.

Contribution

It introduces a novel solid-state memcapacitor design with negative and diverging capacitance based on layered tunneling structures.

Findings

Displays hysteretic charge-voltage behavior

Shows negative and diverging capacitance ranges

Feasible for experimental realization and data storage

Abstract

We suggest a possible realization of a solid-state memory capacitive (memcapacitive) system. Our approach relies on the slow polarization rate of a medium between plates of a regular capacitor. To achieve this goal, we consider a multi-layer structure embedded in a capacitor. The multi-layer structure is formed by metallic layers separated by an insulator so that non-linear electronic transport (tunneling) between the layers can occur. The suggested memcapacitor shows hysteretic charge-voltage and capacitance-voltage curves, and both negative and diverging capacitance within certain ranges of the field. This proposal can be easily realized experimentally, and indicates the possibility of information storage in memcapacitive devices.