The Effected Oxide Capacitor in CMOS Structure of Integrated Circuit Level 5 Micrometer Technology

TL;DR

This paper presents the design and analysis of an oxide capacitor within a CMOS structure at 5 micrometer technology, focusing on capacitance values and layer configurations.

Contribution

It introduces a specific oxide capacitor design in CMOS technology with detailed capacitance measurements and layer configurations at 5 micrometers.

Findings

Capacitance between aluminum and p+ silicon: 28.62 pF

Capacitance between aluminum and n+ silicon: 29.55 pF

Density value with second aluminum layer: 16 pF

Abstract

This article is present the effected oxide capacitor in CMOS structure of integrated circuit level 5 micrometer technology. It has designed and basic structure of MOS diode. It establish with aluminum metallization layer by sputtering method, oxide insulator layer mode from silicon dioxide, n+ and p+ semiconductor layer, it has high capacitance concentrate. From the MOS diode structure silicon dioxide thickness 0.5 micrometer, it will get capacitance between aluminum metal layer and p+ semiconductor at 28.62 pF, the capacitance between aluminum metal layer and n+ semiconductor at 29.55 pF. In this article establish second metal layer for measurement density values of first aluminum metal layer with second aluminum metal layer, it has density values at 16 pF.