An Improved Implementation of Grain

TL;DR

This paper enhances the Grain stream cipher's hardware efficiency by converting its NLFSR from Fibonacci to Galois configuration and adding a clock division, doubling throughput without increasing area.

Contribution

It introduces a novel Galois configuration for Grain's NLFSR and a clock division technique to significantly improve hardware throughput.

Findings

Doubling the throughput of Grain cipher architectures

No additional area penalty incurred

Effective transformation from Fibonacci to Galois configuration

Abstract

A common approach to protect confidential information is to use a stream cipher which combines plain text bits with a pseudo-random bit sequence. Among the existing stream ciphers, Non-Linear Feedback Shift Register (NLFSR)-based ones provide the best trade-off between cryptographic security and hardware efficiency. In this paper, we show how to further improve the hardware efficiency of Grain stream cipher. By transforming the NLFSR of Grain from its original Fibonacci configuration to the Galois configuration and by introducing a clock division block, we double the throughput of the 80 and 128-bit key 1bit/cycle architectures of Grain with no area penalty.