A Fault-tolerant Structure for Reliable Multi-core Systems Based on Hardware-Software Co-design

TL;DR

This paper proposes a hardware-software co-designed fault-tolerant architecture for multi-core systems that reduces hardware and time redundancy, enhancing reliability efficiently.

Contribution

It introduces a novel fault-tolerant architecture combining hardware and software that uses fewer resources and less time than traditional methods.

Findings

Uses less than 33% hardware resources compared to TMR

Reduces fault-tolerance time overhead by less than 50%

Suitable for high-reliability multi-core systems

Abstract

To cope with the soft errors and make full use of the multi-core system, this paper gives an efficient fault-tolerant hardware and software co-designed architecture for multi-core systems. And with a not large number of test patterns, it will use less than 33% hardware resources compared with the traditional hardware redundancy (TMR) and it will take less than 50% time compared with the traditional software redundancy (time redundant).Therefore, it will be a good choice for the fault-tolerant architecture for the future high-reliable multi-core systems.