A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding

TL;DR

This paper presents a novel VLSI architecture for soft-input soft-output sphere decoding in MIMO systems, achieving efficient hardware implementation with minimal area and frequency trade-offs.

Contribution

It introduces the first VLSI architecture for SISO sphere decoding using a single tree-search approach, maintaining high throughput with modest area and frequency impacts.

Findings

57% area increase for 4x4 16-QAM system

34% frequency degradation for the proposed architecture

Single-node-per-cycle execution maintained

Abstract

Multiple-input multiple-output (MIMO) wireless transmission imposes huge challenges on the design of efficient hardware architectures for iterative receivers. A major challenge is soft-input soft-output (SISO) MIMO demapping, often approached by sphere decoding (SD). In this paper, we introduce the - to our best knowledge - first VLSI architecture for SISO SD applying a single tree-search approach. Compared with a soft-output-only base architecture similar to the one proposed by Studer et al. in IEEE J-SAC 2008, the architectural modifications for soft input still allow a one-node-per-cycle execution. For a 4x4 16-QAM system, the area increases by 57% and the operating frequency degrades by 34% only.