Plans for PANDA Online Computing
Jens Soeren Lange (1), Dapeng Jin (2), Daniel Kirschner (1), Andreas, Kopp (1), Wolfgang Kuehn (1), Johannes Lang (1), Lu Li (2), Ming Liu (1),, ZhenAn Liu (2), David Muenchow (1), Tiago Perez (1), Johannes Roskoss (1),, Qiang Wang (2), Hao Xu (2), and Shuo Yang (1)
TL;DR
The PANDA experiment's online system processes streaming data at 280 GB/s, using FPGA-based reconstruction algorithms to reduce data volume by approximately 800 times without hardware triggers.
Contribution
This paper presents a novel FPGA-based data reduction system for the PANDA experiment's high-bandwidth streaming data without hardware triggers.
Findings
Achieves a data reduction factor of ~800
Processes 280 GB/s streaming data in real-time
Uses FPGA-based reconstruction algorithms
Abstract
The PANDA experiment will not use any hardware trigger, i.e. all raw data are streaming in the data acquisition with a bandwidth of ~280 GB/s. The PANDA Online System is designed to perform data reduction by a factor of ~800 by reconstruction algorithms programmed in VHDL (Very High Speed Integrated Circuit Hardware Description Language) on FPGAs (Field Programmable Gate Arrays).
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