Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA

TL;DR

This paper presents a novel FPGA-based implementation of AES that leverages self-partial and dynamic reconfiguration to enhance security, performance, and versatility in embedded cryptographic systems.

Contribution

It introduces an innovative FPGA architecture utilizing self-partial and dynamic reconfiguration for efficient and secure AES implementation in embedded systems.

Findings

Dynamic reconfiguration improves cryptographic performance.

Self-reconfiguring FPGA enhances security and flexibility.

Reduced hardware area through selective reconfiguration.

Abstract

This paper addresses efficient hardware/software implementation approaches for the AES (Advanced Encryption Standard) algorithm and describes the design and performance testing algorithm for embedded system. Also, with the spread of reconfigurable hardware such as FPGAs (Field Programmable Gate Array) embedded cryptographic hardware became cost-effective. Nevertheless, it is worthy to note that nowadays, even hardwired cryptographic algorithms are not so safe. From another side, the self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. Hardware acceleration significantly increases the performance of embedded systems built on programmable logic. Allowing a FPGA-based MicroBlaze processor to self-select the coprocessors uses can help reduce area requirements and increase a system's versatility. The architecture proposed in this paper is an optimal hardware implementation algorithm and takes dynamic partially reconfigurable of FPGA. This implementation is good solution to preserve confidentiality and accessibility to the information in the numeric communication.