Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures

TL;DR

This paper introduces a comprehensive framework for designing and simulating Network on Chip based turbo decoder architectures, optimizing parameters like topology, parallelism, message rate, and routing to enhance throughput and reduce complexity.

Contribution

It provides a systematic analysis of design parameters and identifies optimal topologies and strategies for high-throughput, low-overhead turbo decoder architectures on Network on Chip platforms.

Findings

Generalized de-Bruijn and Kautz topologies are most suitable for high throughput with low complexity.

Different configurations can minimize network area overhead based on throughput needs.

The framework enables tailored design choices for efficient turbo decoder implementations.

Abstract

This work proposes a general framework for the design and simulation of network on chip based turbo decoder architectures. Several parameters in the design space are investigated, namely the network topology, the parallelism degree, the rate at which messages are sent by processing nodes over the network and the routing strategy. The main results of this analysis are: i) the most suited topologies to achieve high throughput with a limited complexity overhead are generalized de-Bruijn and generalized Kautz topologies; ii) depending on the throughput requirements different parallelism degrees, message injection rates and routing algorithms can be used to minimize the network area overhead.