Function Interface Models for Hardware Compilation: Types, Signatures, Protocols

TL;DR

This paper addresses the challenge of hardware compilation by proposing a well-defined function interface model inspired by programming language theory, aiming to improve the synthesis of digital circuits from high-level specifications.

Contribution

It introduces a novel function interface model for hardware compilation, bridging programming language theory and digital circuit synthesis.

Findings

Prototype implementation demonstrating the proposed interface model

Examples illustrating improved communication protocols in hardware synthesis

Discussion of how the model addresses existing obstacles in hardware compilation

Abstract

The problem of synthesis of gate-level descriptions of digital circuits from behavioural specifications written in higher-level programming languages (hardware compilation) has been studied for a long time yet a definitive solution has not been forthcoming. The argument of this essay is mainly methodological, bringing a perspective that is informed by recent developments in programming-language theory. We argue that one of the major obstacles in the way of hardware compilation becoming a useful and mature technology is the lack of a well defined function interface model, i.e. a canonical way in which functions communicate with arguments. We discuss the consequences of this problem and propose a solution based on new developments in programming language theory. We conclude by presenting a prototype implementation and some examples illustrating our principles.