Universal zero-bias conductance for the single electron transistor. II: Comparison with numerical results

TL;DR

This paper uses numerical renormalization-group methods to validate a universal conductance mapping in single-electron transistors, showing excellent agreement in the Kondo regime and accurate low-temperature predictions in the mixed-valence regime.

Contribution

It demonstrates the effectiveness of a recently derived linear mapping for conductance across different regimes in quantum dots, supported by numerical results.

Findings

Excellent agreement with the mapping in the Kondo regime

Accurate description of low-temperature conductance tail in mixed-valence regime

Unified view of conduction in single-electron transistors

Abstract

A numerical renormalization-group survey of the zero-bias electrical conductance through a quantum dot embedded in the conduction path of a nanodevice is reported. The results are examined in the light of a recently derived linear mapping between the temperature-dependent conductance and the universal function describing the conductance for the symmetric Anderson model. A gate potential applied to the conduction electrons is known to change markedly the transport properties of a quantum dot side-coupled to the conduction path; in the embedded geometry here discussed, a similar potential is shown to affect only quantitatively the temperature dependence of the conductance. As expected, in the Kondo regime the numerical results are in excellent agreement with the mapped conductances. In the mixed-valence regime, the mapping describes accurately the low-temperature tail of the conductance. The mapping is shown to provide a unified view of conduction in the single-electron transistor.