Fault tolerant architectures for superconducting qubits

TL;DR

This paper reviews recent theoretical advances in fault-tolerant quantum computing architectures, emphasizing surface codes for superconducting qubits, which could enable practical quantum error correction with high error thresholds.

Contribution

It highlights the potential of surface codes in superconducting qubits and discusses hardware developments needed for fault-tolerant quantum computation.

Findings

Surface codes can achieve error thresholds around 0.75%.

Planar architectures using surface codes are promising for logical gate operations.

Hardware demonstrations are crucial next steps for fault-tolerant superconducting qubits.

Abstract

In this short review, I draw attention to new developments in the theory of fault tolerance in quantum computation that may give concrete direction to future work in the development of superconducting qubit systems. The basics of quantum error correction codes, which I will briefly review, have not significantly changed since their introduction fifteen years ago. But an interesting picture has emerged of an efficient use of these codes that may put fault tolerant operation within reach. It is now understood that two dimensional surface codes, close relatives of the original toric code of Kitaev, can be adapted to effectively perform logical gate operations in a very simple planar architecture, with error thresholds for fault tolerant operation simulated to be 0.75%. This architecture uses topological ideas in its functioning, but it is not 'topological quantum computation' -- there are no non-abelian anyons in sight. I offer some speculations on the crucial pieces of superconducting hardware that could be demonstrated in the next couple of years that would be clear stepping stones towards this surface-code architecture.