Introducing a Performance Model for Bandwidth-Limited Loop Kernels

TL;DR

This paper introduces a performance model for bandwidth-limited loop kernels based on cache microarchitecture analysis, enabling accurate performance prediction and understanding of memory hierarchy impacts.

Contribution

The paper presents a novel performance model specifically designed for bandwidth-limited loop kernels, validated on modern x86 architectures.

Findings

Accurate performance prediction for memory operations

Insights into memory hierarchy performance contributions

Model validated on multiple modern architectures

Abstract

We present a performance model for bandwidth limited loop kernels which is founded on the analysis of modern cache based microarchitectures. This model allows an accurate performance prediction and evaluation for existing instruction codes. It provides an in-depth understanding of how performance for different memory hierarchy levels is made up. The performance of raw memory load, store and copy operations and a stream vector triad are analyzed and benchmarked on three modern x86-type quad-core architectures in order to demonstrate the capabilities of the model.