Output Width Signal Control In Asynchronous Digital Systems Using External Clock Signal

TL;DR

This paper proposes a method to control output signal width in asynchronous digital systems by using an external clock signal, addressing timing delays and signal duration issues.

Contribution

It introduces a novel approach utilizing an external clock signal to manage output signal width in asynchronous systems, improving timing reliability.

Findings

Effective control of output signal width achieved

Method reduces timing delays in asynchronous systems

Demonstrated using an example system

Abstract

In present paper, I propose a method for resolving the timing delays for output signals from an asynchronous sequential system. It will be used an example of an asynchronous sequential system that will set up an output signal when an input signal will be set up. The width of the output signal depends on the input signal width, and in this case it is very short. There are many synthesis methods, like using a RC group system, a monostable system in design of the asynchronous digital system or using an external clock signal, CK. In this paper will be used an external clock signal, CK.