A new 130nm F.E readout chip for microstrip detectors

TL;DR

This paper presents a compact 130nm CMOS readout chip with 88 channels designed for silicon strip detectors in future collider experiments, integrating full analog processing and digital readout in a small form factor.

Contribution

It introduces a novel highly integrated 130nm CMOS readout chip specifically designed for silicon strip detectors in linear collider applications.

Findings

Chip includes 88 channels of analog and digital processing

The chip measures 5x10mm2 with 80% analog area

Designed for future International Linear Collider experiments

Abstract

In the context of the Silicon tracking for a Linear Collider (SiLC) R&D collaboration, a highly compact mixed-signal chip has been designed in 130nm CMOS technology intended to read Silicon strip detectors for the experiments at the future International Linear Collider. The chip includes eighty eight channels of a full analog signal processing chain and analog to digital conversion with the corresponding digital controls and readout channels. The chip is 5x10mm2 where the analog implementation represents 4/5 of the total Silicon area.