Development of Readout ASIC for FPCCD Vertex Detector

TL;DR

This paper reports on the development and testing of a readout ASIC for the FPCCD vertex detector, aiming to improve performance for the ILC by validating its functionality at slow readout speeds.

Contribution

It introduces a new readout ASIC prototype for the FPCCD vertex detector and presents its performance validation at slow readout speeds.

Findings

ASIC works correctly at 1.5 Mpix/sec

Performance study ongoing for different speeds

Supports FPCCD vertex detector development

Abstract

We develop the vertex detector for the international linear collider (ILC) using the FPCCD (Fine Pixel CCD), whose pixel size is 5 x 5 um2. Together with the FPCCD sensor, a prototype of the readout ASIC was developed in 2008. The readout ASIC was confirmed to work correctly at slow readout speed (1.5 Mpix/sec). In this letter, we describe the status of the performance study for the readout ASIC.