Nonvolatile SRAM architecture using MOSFET-based spin-transistors

TL;DR

This paper introduces a novel nonvolatile SRAM architecture utilizing MOSFET-based spin-transistors called PS-MOSFETs, enabling electrical data storage and automatic restoration without affecting standard SRAM performance.

Contribution

The paper presents a new NV-SRAM design using PS-MOSFETs that integrates magnetic tunnel junctions for nonvolatile storage, based on recent MRAM technology advancements.

Findings

Successful circuit simulation of NV-SRAM with PS-MOSFETs

Low power consumption demonstrated in simulations

No impact on conventional SRAM operation performance

Abstract

The authors proposed and computationally analyzed nonvolatile static random access memory (NV-SRAM) architecture using metal-oxide-semiconductor field-effect transistor (MOSFET) type of spin-transistors referred to as pseudo-spin-MOSFET (PS-MOSFET). PS-MOSFET is a new circuit approach to reproduce the functions of spin-transistors, based on recently progressed magnetoresistive random access memory (MRAM) technology. The proposed NV-SRAM cell can be simply configured by connecting two PS-MOSFETs to the storage nodes of a standard SRAM cell. The logic information of the storage nodes can be electrically stored into the magnetic tunnel junctions (MTJs) of the PS-MOSFETs by current-induced magnetization switching (CIMS), and the stored information is automatically restored when the inverter loop circuit wakes up. In addition, the proposed NV-SRAM cell has no influence on the performance of normal SRAM operations. Low power dissipation and high degree of freedom of MTJ design are also remarkable features for NV-SRAM using PS-MOSFETs.