Performance Analysis of 60nm gate length III-V InGaAs HEMTs: Simulations vs. experiments
Neophytos Neophytou, Titash Rakshit, Mark S. Lundstrom

TL;DR
This paper compares experimental data of 60nm InGaAs HEMTs with quantum ballistic simulations, revealing discrepancies at high voltages and insights into device limitations and carrier dynamics.
Contribution
It introduces a quantum ballistic model for InGaAs HEMTs and compares it with experimental data, highlighting the effects of parasitic resistance and non-idealities.
Findings
Ballistic model describes devices with different oxide thicknesses and lengths.
Simulations overestimate on-current at high gate voltages.
Device operation is below the ballistic limit, indicating non-ideal effects.
Abstract
An analysis of recent experimental data for high-performance In0.7Ga0.3As high electron mobility transistors (HEMTs) is presented. Using a fully quantum mechanical, ballistic model, we simulate In0.7Ga0.3As HEMTs with gate lengths of LG = 60nm, 85, and 135 nm and compare the result to the measured I-V characteristics including draininduced barrier lowering, sub-threshold swing, and threshold voltage variation with gate insulator thickness, as well as on-current performance. To first order, devices with three different oxide thicknesses and channel lengths can all be described by our ballistic model with appropriate values of parasitic series resistance. For high gate voltages, however, the ballistic simulations consistently overestimate the measured on-current, and they do not show the experimentally observed decrease in on-current with increasing gate length. With no parasitic series…
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