A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks

TL;DR

This paper introduces a reconfigurable asynchronous FPGA logic block designed to resist side-channel attacks by removing synchronization and supporting multiple control and data styles.

Contribution

It presents a novel programmable logic block for asynchronous FPGAs that enhances security against side-channel attacks and supports various asynchronous control styles.

Findings

Resistant to side-channel attacks due to asynchronous design.

Supports multiple asynchronous control and data styles.

Enhances security in cryptographic hardware implementations.

Abstract

Side-channel attacks are efficient attacks against cryptographic devices. They use only quantities observable from outside, such as the duration and the power consumption. Attacks against synchronous devices using electric observations are facilitated by the fact that all transitions occur simultaneously with some global clock signal. Asynchronous control remove this synchronization and therefore makes it more difficult for the attacker to insulate \emph{interesting intervals}. In addition the coding of data in an asynchronous circuit is inherently more difficult to attack. This article describes the Programmable Logic Block of an asynchronous FPGA resistant against \emph{side-channel attacks}. Additionally it can implement different styles of asynchronous control and of data representation.