A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization
Aaron Parsons, Donald Backer, Henry Chen, Pierre Droz, Terry Filiba,, Jason Manley, David MacMahon, Peter McMahon, Arash Parsa, Andrew Siemion, Dan, Werthimer, and Melvyn Wright

TL;DR
This paper introduces a scalable, flexible FPGA-based correlator architecture utilizing modular hardware, open-source libraries, and Ethernet data packetization, enabling efficient processing for large radio telescope arrays.
Contribution
It presents a novel, scalable correlator design using standard Ethernet switches and open-source FPGA libraries, reducing implementation time and costs for large-scale radio astronomy signal processing.
Findings
Successfully deployed a 16-antenna correlator system
Achieved processing of 200-MHz bandwidth with 4-bit resolution
Demonstrated flexibility and scalability of the architecture
Abstract
A new generation of radio telescopes is achieving unprecedented levels of sensitivity and resolution, as well as increased agility and field-of-view, by employing high-performance digital signal processing hardware to phase and correlate large numbers of antennas. The computational demands of these imaging systems scale in proportion to BMN^2, where B is the signal bandwidth, M is the number of independent beams, and N is the number of antennas. The specifications of many new arrays lead to demands in excess of tens of PetaOps per second. To meet this challenge, we have developed a general purpose correlator architecture using standard 10-Gbit Ethernet switches to pass data between flexible hardware modules containing Field Programmable Gate Array (FPGA) chips. These chips are programmed using open-source signal processing libraries we have developed to be flexible, scalable, and…
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