Easily testable logical networks based on a 'widened long flip-flop'
Nick Stukach

TL;DR
This paper introduces a novel approach to testing complex digital systems by using limited connections in logical networks, addressing testing complexity, tester testing, and defect masking issues.
Contribution
It proposes a new method based on limitations in logical gate connections to improve testability of digital networks with multiple stuck-at faults.
Findings
Reduces testing complexity for complex digital equipment
Enhances detection of multiple stuck-at faults
Addresses defect masking problems effectively
Abstract
The article describes an attempt to solve at once three basic problems arising at testing a complex digital equipment for defects: 1) the problem of an exponential increasing of the complexity of testing the equipment with the complexity of the equipment; 2) the problem of testing of the tester; 3) the problem of a mutual masking of defects. The proposed solution is nothing more than using certain limitations for connections between usual logical gates. Arbitrary multiple stuck-at-faults are supposed as defects.
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Taxonomy
TopicsEmbedded Systems Design Techniques · VLSI and Analog Circuit Testing · Computability, Logic, AI Algorithms
