Simulation of the Lattice QCD and Technological Trends in Computation

TL;DR

This paper evaluates the performance and efficiency of various modern computational architectures for simulating Lattice QCD, highlighting technological trends and identifying performance bottlenecks to guide future scientific computing efforts.

Contribution

It provides a comparative assessment of heterogeneous computing architectures for Lattice QCD and projects future performance improvements based on technological trends.

Findings

Performance trade-offs vary across architectures.

Identified limiting factors for Lattice QCD simulations.

Projected improvements suggest potential for enhanced computational efficiency.

Abstract

Simulation of Lattice QCD is a challenging computational problem. Currently, technological trends in computation show multiple divergent models of computation. We are witnessing homogeneous multi-core architectures, the use of accelerator on-chip or off-chip, in addition to the traditional architectural models. On the verge of this technological abundance, assessing the performance trade-offs of computing nodes based on these technologies is of crucial importance to many scientific computing applications. In this study, we focus on assessing the efficiency and the performance expected for the Lattice QCD problem on representative architectures and we project the expected improvement on these architectures and their impact on performance for Lattice QCD. We additionally try to pinpoint the limiting factors for performance on these architectures.