Design and Implementation a 8 bits Pipeline Analog to Digital Converter in the Technology 0.6 \mu m CMOS Process

TL;DR

This paper presents an 8-bit pipeline ADC designed in 0.6 μm CMOS technology, achieving high sampling rate and low power consumption with precise circuit techniques and simulation results.

Contribution

The paper introduces a novel 8-bit pipeline ADC design with specific circuit techniques and simulation validation in 0.6 μm CMOS technology.

Findings

DNL and INL of 0.75 LSB in worst case

SNDR of 44.86 dB achieved

Power dissipation of 75.47 mW

Abstract

This paper describes a 8 bits, 20 Msamples/s pipeline analog-to-digital converter implemented in 0.6 \mu m CMOS technology with a total power dissipation of 75.47 mW. Circuit techniques used include a precise comparator, operational amplifier and clock management. A switched capacitor is used to sample and multiplying at each stage. Simulation a worst case DNL and INL of 0.75 LSB. The design operate at 5 V dc. The ADC achieves a SNDR of 44.86 dB. keywords : pipeline, switched capacitor, clock management