Electron mobility in silicon nanowires

TL;DR

This study computes electron mobility in silicon nanowires, revealing how phonon and surface roughness effects vary with wire width and transport regime, highlighting the transition from 2D to 1D behavior.

Contribution

It provides a detailed analysis of low-field and high-field mobility components in silicon nanowires, emphasizing the effects of wire width and surface roughness.

Findings

Phonon-limited mobility decreases as wire width shrinks.

Surface-roughness-limited mobility increases at high fields with decreasing width.

Volume inversion influences mobility behavior at small scales.

Abstract

The low-field electron mobility in rectangular silicon nanowire (SiNW) transistors was computed using a self-consistent Poisson-Schr\"{o}dinger-Monte Carlo solver. The behavior of the phonon-limited and surface-roughness-limited components of the mobility was investigated by decreasing the wire width from 30 nm to 8 nm, the width range capturing a crossover between two-dimensional (2D) and one-dimensional (1D) electron transport. The phonon-limited mobility, which characterizes transport at low and moderate transverse fields, is found to decrease with decreasing wire width due to an increase in the electron-phonon wavefunction overlap. In contrast, the mobility at very high transverse fields, which is limited by surface roughness scattering, increases with decreasing wire width due to volume inversion. The importance of acoustic phonon confinement is also discussed briefly.