Fast trigger logic with digitized time information

TL;DR

This paper introduces a high-resolution, dead-time-less trigger logic method implemented on FPGA, enabling precise veto conditions at the first trigger level for high-rate experiments involving fast signals.

Contribution

The paper presents a novel FPGA-based implementation for high-resolution, dead-time-less trigger logic using digitized timing information, suitable for rare decay experiments.

Findings

High time resolution trigger logic achieved

Dead-time-less implementation demonstrated

Effective veto conditions for rare decay experiments

Abstract

We present a method for the evaluation, at the first level of trigger, of logical conditions with high time resolution, using the digitized times of fast signals delivered in the detectors of high rate experiments. We describe a dead-time-less implementation of this method on a commercial Field Programmable Gate Array (FPGA). By virtue of its features, the method offers an excellent solution to the problem of including veto conditions in the first level of trigger for experiments on rare decays.