Testability of Reversible Iterative Logic Arrays
Avik Chakraborty

TL;DR
This paper investigates the testability of reversible iterative logic arrays, demonstrating their constant-testability and optimal-testability, and presents efficient test generation algorithms applicable to various dimensions.
Contribution
It introduces the concepts of C-Testability, O-Testability, and U-Testability for reversible ILAs and provides cycle-based algorithms for efficient test generation.
Findings
Reversible ILAs are proven to be C-Testable and O-Testable.
Test set size remains constant for certain ILAs regardless of size.
Efficient test generation algorithms are developed for 1-D and 2-D ILAs.
Abstract
Iterative Logic Arrays (ILAs) are ideal as VLSI sub-systems because of their regular structure and its close resemblance with FPGAs (Field Programmable Gate Arrays). Reversible circuits are of interest in the design of very low power circuits where energy loss implied by high frequency switching is not of much consideration. Reversibility is essential for Quantum Computing. This paper examines the testability of Reversible Iterative Logic Arrays (ILAs) composed of reversible k-CNOT gates. For certain ILAs it is possible to find a test set whose size remains constant irrespective of the size of the ILA, while for others it varies with array size. Former type of ILAs is known as Constant-Testable, i.e. C-Testable. It has been shown that Reversible Logic Arrays are C-Testable and size of test set is equal to number of entries in cells truth table implying that the reversible ILAs are also…
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Taxonomy
TopicsLow-power high-performance VLSI design · VLSI and Analog Circuit Testing · Quantum Computing Algorithms and Architecture
