High Density Through Silicon Via (TSV)

TL;DR

This paper discusses the development and advantages of Through Silicon Via (TSV) technology by Silex, highlighting its high-density capabilities, integration benefits, and industry adoption for advanced MEMS and wafer-level packaging.

Contribution

It introduces the TSV formation process, presents novel solutions enabled by the technology, and discusses its impact on MEMS integration and industry standards.

Findings

TSV pitch as small as 30 micrometers

Enables wafer-level packaging and die size reduction

Industry adoption with qualified volume manufacturing

Abstract

The Through Silicon Via (TSV) process developed by Silex provides down to 30 micrometers pitch for through wafer connections in up to 600 micrometers thick substrates. Integrated with MEMS designs it enables significantly reduced die size and true "Wafer Level Packaging" - features that are particularly important in consumer market applications. The TSV technology also enables integration of advanced interconnect functions in optical MEMS, sensors and microfluidic devices. In addition the Via technology opens for very interesting possibilities considering integration with CMOS processing. With several companies using the process already today, qualified volume manufacturing in place and a line-up of potential users, the process is becoming a standard in the MEMS industry. We provide a introduction to the via formation process and also present some on the novel solutions made available by the technology.