Top-gated graphene field-effect-transistors formed by decomposition of SiC

TL;DR

This paper demonstrates the fabrication of top-gated graphene FETs on SiC substrates with high mobility, confirming the formation of multiple graphene layers and their unique transport properties.

Contribution

It introduces a method to create graphene FETs on SiC with high mobility using thermal decomposition and SiO2 gate dielectric.

Findings

High electron mobility of 5400 cm2/Vs achieved

Observation of Dirac Fermions confirms graphene quality

Successful formation of multiple graphene layers on SiC

Abstract

Top-gated, few-layer graphene field-effect transistors (FETs) fabricated on thermally-decomposed semi-insulating 4H-SiC substrates are demonstrated. Physical vapor deposited SiO2 is used as the gate dielectric. A two-dimensional hexagonal arrangement of carbon atoms with the correct lattice vectors, observed by high-resolution scanning tunneling microscopy, confirms the formation of multiple graphene layers on top of the SiC substrates. The observation of n-type and p-type transition further verifies Dirac Fermions unique transport properties in graphene layers. The measured electron and hole mobility on these fabricated graphene FETs are as high as 5400 cm2/Vs and 4400 cm2/Vs respectively, which are much larger than the corresponding values from conventional SiC or silicon.