Efficient implementation of GALS systems over commercial synchronous FPGAs: a new approach

TL;DR

This paper introduces a novel approach for implementing GALS systems on commercial synchronous FPGAs, reducing logic overhead and enabling advanced electromagnetic interference mitigation and environmental adaptation.

Contribution

It proposes a 2-phase, bundled data parity protocol and a smart delay selection method for efficient GALS implementation on FPGAs.

Findings

Reduced logic overhead in GALS FPGA implementations

Enhanced electromagnetic interference mitigation capabilities

Adaptive delay selection improves system robustness

Abstract

The new vision presented is aimed to overcome the logic overhead issues that previous works exhibit when applying GALS techniques to programmable logic devices. The proposed new view relies in a 2-phase, bundled data parity based protocol for data transfer and clock generation tasks. The ability of the introduced methodology for smart real-time delay selection allows the implementation of a variety of new methodologies for electromagnetic interference mitigation and device environment changes adaptation.