High-Yield of Memory Elements from Carbon Nanotube Field-Effect Transistors with Atomic Layer Deposited Gate Dielectric

TL;DR

This study demonstrates that by carefully designing the gate dielectric with atomic layer deposition of HfO₂ and TiO₂, it is possible to produce CNT FETs with consistent and controlled hysteresis, improving their potential for nano-electronic applications.

Contribution

The paper introduces a novel triple-layer dielectric configuration using ALD to achieve uniform and predictable hysteresis in CNT FETs, addressing a key variability issue.

Findings

Achieved consistent hysteresis in CNT FETs with ALD dielectric layers.

Provided statistical analysis of hysteresis across 94 samples.

Demonstrated control over memory effects through dielectric design.

Abstract

Carbon nanotube field-effect transistors (CNT FETs) have been proposed as possible building blocks for future nano-electronics. But a challenge with CNT FETs is that they appear to randomly display varying amounts of hysteresis in their transfer characteristics. The hysteresis is often attributed to charge trapping in the dielectric layer between the nanotube and the gate. This study includes 94 CNT FET samples, providing an unprecedented basis for statistics on the hysteresis seen in five different CNT-gate configurations. We find that the memory effect can be controlled by carefully designing the gate dielectric in nm-thin layers. By using atomic layer depositions (ALD) of HfO$_{2}$ and TiO$_{2}$ in a triple-layer configuration, we achieve the first CNT FETs with consistent and narrowly distributed memory effects in their transfer characteristics.