Very Fast Chip-level Thermal Analysis
K. Nakabayashi, T. Nakabayashi, K. Nakajima

TL;DR
This paper introduces a rapid chip-level thermal analysis method that extends 2D Laplace equation solutions to multi-material boards, demonstrating significantly faster performance and higher accuracy than commercial tools.
Contribution
The paper presents a novel, faster thermal analysis technique for VLSI chips that improves upon existing methods by extending Laplace equation solutions to complex multi-material scenarios.
Findings
Our method runs 5.8 to 8.9 times faster than commercial tools.
It achieves residuals smaller by 5 to 10 times.
The technique effectively handles four-material thermal analysis on motherboards.
Abstract
We present a new technique of VLSI chip-level thermal analysis. We extend a newly developed method of solving two dimensional Laplace equations to thermal analysis of four adjacent materials on a mother board. We implement our technique in C and compare its performance to that of a commercial CAD tool. Our experimental results show that our program runs 5.8 and 8.9 times faster while keeping smaller residuals by 5 and 1 order of magnitude, respectively.
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Taxonomy
Topics3D IC and TSV technologies · VLSI and FPGA Design Techniques · Low-power high-performance VLSI design
