Reducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by Means of Heuristic Scheduling Algorithm

TL;DR

This paper introduces a heuristic scheduling algorithm for VLSI CMOS digital circuits that balances power dissipation across units, effectively reducing both average and peak temperatures without compromising system throughput.

Contribution

The paper proposes a novel BPD heuristic scheduling algorithm that balances power dissipation during task assignment in VLSI CMOS systems, improving thermal management.

Findings

Reduces average temperatures of VLSI CMOS circuits

Lowers peak temperatures during operation

Maintains system throughput

Abstract

This paper presents a BPD (Balanced Power Dissipation) heuristic scheduling algorithm applied to VLSI CMOS digital circuits/systems in order to reduce the global computational demand and provide balanced power dissipation of computational units of the designed digital VLSI CMOS system during the task assignment stage. It results in reduction of the average and peak temperatures of VLSI CMOS digital circuits. The elaborated algorithm is based on balanced power dissipation of local computational (processing) units and does not deteriorate the throughput of the whole VLSI CMOS digital system.