A Computational Study of Vertical Partial Gate Carbon Nanotube FETs

TL;DR

This study simulates vertical partial gate carbon nanotube FETs, revealing that gate underlap improves transistor performance by reducing leakage, and that increasing CNT diameter boosts both on current and leakage, with potential improvements from high-k insulators.

Contribution

It introduces a self-consistent atomistic simulation of vertical partial gate CNTFETs, highlighting the benefits of gate underlap and the effects of CNT diameter and insulator properties.

Findings

Gate underlap suppresses ambipolar conduction.

Partial gate design reduces leakage current.

Increasing CNT diameter enhances on current and leakage.

Abstract

A vertical partial gate carbon nanotube (CNT) field-effect transistor (FET), which is amenable to the vertical CNT growth process and offers the potential for a parallel CNT array channel, is simulated using a self-consistent atomistic approach. We show that the underlap between the gate and the bottom electrode (required for isolation between electrodes) is advantageous for transistor operation because it suppresses ambipolar conduction. A vertical CNTFET with a gate length that covers only 1/6 of the channel length has a much smaller minimum leakage current than one without underlap, while maintaining comparable on current. Both n-type and p-type transistor operations with balanced performance metrics can be achieved on a single partial gate FET by using proper bias schemes. Even with a gate underlap, it is demonstrated that increasing the CNT diameter still leads to a simultaneous increase of on current and minimum leakage current. Along with a partial gate, the simulated transistor features a significant amount of air between the surface of the channel CNT and the gate insulator, as is caused by the vertical CNT growth process. Filing this pore with a high-k insulator is shown to have the potential to decrease the on current, due to electrostatic phenomena at the source-channel contact.