Optimal Memoryless Encoding for Low Power Off-Chip Data Buses

TL;DR

This paper introduces the first provably optimal, explicit memoryless encoding schemes for off-chip data buses that minimize power consumption by reducing bit transitions, demonstrating that clock access does not enhance their effectiveness.

Contribution

It provides the first polynomial-time constructible, provably optimal memoryless codes for minimizing bit transitions in off-chip buses, establishing their fundamental limitations.

Findings

Optimal memoryless codes are explicitly constructed and polynomial-time computable.

Having a clock does not improve the power minimization capability of these codes.

The results set a theoretical benchmark for power-efficient bus encoding schemes.

Abstract

Off-chip buses account for a significant portion of the total system power consumed in embedded systems. Bus encoding schemes have been proposed to minimize power dissipation, but none has been demonstrated to be optimal with respect to any measure. In this paper, we give the first provably optimal and explicit (polynomial-time constructible) families of memoryless codes for minimizing bit transitions in off-chip buses. Our results imply that having access to a clock does not make a memoryless encoding scheme that minimizes bit transitions more powerful.