Au-SN Flip-Chip Solder Bump for Microelectronic and Optoelectronic Applications

TL;DR

This study introduces a co-electroplating method to deposit eutectic Au-Sn solder directly onto wafers for microelectronic and optoelectronic applications, simplifying the process and eliminating flux use.

Contribution

It demonstrates a novel co-electroplating technique for Au-Sn solder deposition with controlled phase formation and interface microstructure without flux.

Findings

Successful direct plating of Au-Sn solder at eutectic composition.

Formation of specific intermetallic compounds depending on reflow temperature.

Increased IMC layer thickness and coarsening with longer reflow times.

Abstract

As an alternative to the time-consuming solder pre-forms and pastes currently used, a co-electroplating method of eutectic Au-Sn alloy was used in this study. Using a co-electroplating process, it was possible to plate the Au-Sn solder directly onto a wafer at or near the eutectic composition from a single solution. Two distinct phases, Au5Sn and AuSn, were deposited at a composition of 30at.%Sn. The Au-Sn flip-chip joints were formed at 300 and 400 degrees without using any flux. In the case where the samples were reflowed at 300 degrees, only an (Au,Ni)3Sn2 IMC layer formed at the interface between the Au-Sn solder and Ni UBM. On the other hand, two IMC layers, (Au,Ni)3Sn2 and (Au,Ni)3Sn, were found at the interfaces of the samples reflowed at 400 degrees. As the reflow time increased, the thickness of the (Au,Ni)3Sn2 and (Au,Ni)3Sn IMC layers formed at the interface increased and the eutectic lamellae in the bulk solder coarsened.