Parasitic Effects Reduction for Wafer-Level Packaging of RF-Mems

TL;DR

This paper investigates and optimizes wafer-level packaging processes for RF-MEMS to reduce parasitic effects, focusing on substrate properties and via geometry to enhance electrical performance.

Contribution

It introduces an optimized wafer-level bonding process for RF-MEMS that minimizes parasitic effects through simulation and experimental validation.

Findings

Optimized substrate resistivity and thickness reduce parasitic effects.

Via geometry significantly impacts electrical performance.

Simulation results guide the fabrication of test structures.

Abstract

In RF-MEMS packaging, next to the protection of movable structures, optimization of package electrical performance plays a very important role. In this work, a wafer-level packaging process has been investigated and optimized in order to minimize electrical parasitic effects. The RF-MEMS package concept used is based on a wafer-level bonding of a capping silicon substrate to an RF-MEMS wafer. The capping silicon substrate resistivity, substrate thickness and the geometry of through-substrate electrical interconnect vias have been optimized using finite-element electromagnetic simulations (Ansoft HFSS). Test structures for electrical characterization have been designed and after their fabrication, measurement results will be compared with simulations.