Partial Reversible Gates(PRG) for Reversible BCD Arithmetic

TL;DR

This paper introduces Partial Reversible Gates (PRG) to optimize reversible BCD arithmetic circuits by reducing the number of gates and garbage outputs, advancing low-power and quantum computing applications.

Contribution

It proposes the novel concept of partial reversible gates that satisfy reversibility for specific BCD arithmetic cases, improving circuit efficiency.

Findings

Reduces the number of reversible gates needed

Minimizes garbage outputs in BCD circuits

Enhances efficiency for low-power and quantum computing

Abstract

IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Furthermore, in the recent years reversible logic has emerged as a promising computing paradigm having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The major goal in reversible logic is to minimize the number of reversible gates and garbage outputs. Thus, this paper proposes the novel concept of partial reversible gates that will satisfy the reversibility criteria for specific cases in BCD arithmetic. The partial reversible gate is proposed to minimize the number of reversible gates and garbage outputs, while designing the reversible BCD arithmetic circuits.