Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs

TL;DR

This paper introduces a novel FPGA architecture that integrates dedicated multipliers for efficient integer and variable precision floating point multiplication, enhancing performance for multimedia and scientific applications.

Contribution

It proposes replacing existing FPGA multipliers with specialized 24x24 and 24x9 bit multipliers to support multiple floating point precisions efficiently.

Findings

Improved FPGA efficiency for floating point operations

Supports multiple precisions including single, double, and quadruple

Demonstrates suitability for multimedia processing applications

Abstract

In this paper, we propose an architecture/methodology for making FPGAs suitable for integer as well as variable precision floating point multiplication. The proposed work will of great importance in applications which requires variable precision floating point multiplication such as multi-media processing applications. In the proposed architecture/methodology, we propose the replacement of existing 18x18 bit and 25x18 bit dedicated multipliers in FPGAs with dedicated 24x24 bit and 24x9 bit multipliers, respectively. We have proved that our approach of providing the dedicated 24x24 bit and 24x9 bit multipliers in FPGAs will make them efficient for performing integer as well as single precision, double precision, and Quadruple precision floating point multiplications.