On the operating unit size of load/store architectures

TL;DR

This paper investigates how the size of the operating unit in strict load/store architectures influences the set of achievable state transformations, considering instruction set size and thread complexity within Maurer machines.

Contribution

It introduces a strict version of load/store instruction set architectures in Maurer machines and analyzes the impact of operating unit size on state transformation capabilities.

Findings

Transformations depend on operating unit size

Instruction set cardinality affects transformation power

Thread state limits influence achievable transformations

Abstract

We introduce a strict version of the concept of a load/store instruction set architecture in the setting of Maurer machines. We take the view that transformations on the states of a Maurer machine are achieved by applying threads as considered in thread algebra to the Maurer machine. We study how the transformations on the states of the main memory of a strict load/store instruction set architecture that can be achieved by applying threads depend on the operating unit size, the cardinality of the instruction set, and the maximal number of states of the threads.