A Formal Verification Methodology for Checking Data Integrity

TL;DR

This paper introduces a formal verification methodology that simplifies property specification at the block level, enabling systematic and thorough checking of data integrity in complex designs, demonstrated on server platform components.

Contribution

The paper proposes a novel approach to formal verification by breaking down system properties into stereotype properties at the block level for easier specification and verification.

Findings

Identified critical logic bugs quickly during verification.

Verified over 2000 properties related to RAS features.

Enabled non-experts to describe properties easily.

Abstract

Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verification is to define good verification scopes; we should define clearly what to be verified formally upon designs under tests. We considered the following three practical requirements when we defined the scope of formal verification. They are (a) hard to verify (b) small to handle, and (c) easy to understand. Our novel approach is to break down generic properties for system into stereotype properties in block level and to define requirements for Verifiable RTL. Consequently, each designer instead of verification experts can describe properties of the design easily, and formal model checking can be applied systematically and thoroughly to all the leaf modules. During the development of a component chip for server platforms, we focused on RAS (Reliability, Availability, and Serviceability) features and described more than 2000 properties in PSL. As a result of the formal verification, we found several critical logic bugs in a short time with limited resources, and successfully verified all of them. This paper presents a study of the functional verification methodology.