Evaluation of SystemC Modelling of Reconfigurable Embedded Systems

TL;DR

This paper compares the simulation speeds of SystemC models and HDL for embedded systems, demonstrating that SystemC can achieve significantly higher simulation speeds, enabling faster design exploration and software development.

Contribution

It provides a detailed evaluation of pin and cycle accurate SystemC models' simulation speeds compared to HDL, highlighting techniques to enhance simulation performance.

Findings

SystemC models reach up to 150 kHz simulation speed.

Cycle accuracy compromises can increase speed to 500 kHz.

HDL simulation speeds are around 100 Hz.

Abstract

This paper evaluates the use of pin and cycle accurate SystemC models for embedded system design exploration and early software development. The target system is MicroBlaze VanillaNet Platform running MicroBlaze uClinux operating system. The paper compares Register Transfer Level (RTL) Hardware Description Language (HDL) simulation speed to the simulation speed of several different SystemC models. It is shown that simulation speed of pin and cycle accurate models can go up to 150 kHz, compared to 100 Hz range of HDL simulation. Furthermore, utilising techniques that temporarily compromise cycle accuracy, effective simulation speed of up to 500 kHz can be obtained.