A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms

TL;DR

This paper introduces a methodology for partitioning and mapping applications onto hybrid reconfigurable hardware, significantly improving performance by reducing clock cycles in real-world applications like OFDM transmitters and JPEG encoders.

Contribution

It presents a novel partitioning and mapping methodology for heterogeneous reconfigurable platforms, validated with a prototype framework and real-world applications.

Findings

82% reduction in clock cycles for OFDM transmitter

43% performance improvement for JPEG encoder

Applicable to various heterogeneous reconfigurable architectures

Abstract

In this paper, we propose a methodology for partitioning and mapping computational intensive applications in reconfigurable hardware blocks of different granularity. A generic hybrid reconfigurable architecture is considered so as the methodology can be applicable to a large number of heterogeneous reconfigurable platforms. The methodology mainly consists of two stages, the analysis and the mapping of the application onto fine and coarse-grain hardware resources. A prototype framework consisting of analysis, partitioning and mapping tools has been also developed. For the coarse-grain reconfigurable hardware, we use our previous-developed high-performance coarse-grain data-path. In this work, the methodology is validated using two real-world applications, an OFDM transmitter and a JPEG encoder. In the case of the OFDM transmitter, a maximum clock cycles decrease of 82% relative to the ones in an all fine-grain mapping solution is achieved. The corresponding performance improvement for the JPEG is 43%.