MultiNoC: A Multiprocessing System Enabled by a Network on Chip

TL;DR

MultiNoC presents a programmable on-chip multiprocessing platform utilizing a Network on Chip (NoC) for scalable, energy-efficient, and reliable interconnection, enabling execution of sequential or parallel algorithms in embedded systems.

Contribution

It introduces a flexible, low-overhead NoC-based multiprocessing system that supports both sequential and parallel algorithms for embedded applications.

Findings

Efficient, low-area NoC implementation for multiprocessing

Supports execution of both sequential and parallel algorithms

Facilitates the development of 'sea of processors' systems

Abstract

The MultiNoC system implements a programmable on-chip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed interconnection structure is a Network on Chip, or NoC. NoCs are emerging as a viable alternative to increasing demands on interconnection architectures, due to the following characteristics: (i) energy efficiency and reliability; (ii) scalability of bandwidth, when compared to traditional bus architectures; (iii) reusability; (iv) distributed routing decisions. An external host computer feeds MultiNoC with application instructions and data. After this initialization procedure, MultiNoC executes some algorithm. After finishing execution of the algorithm, output data can be read back by the host. Sequential or parallel algorithms conveniently adapted to the MultiNoC structure can be executed. The main motivation to propose this design is to enable the investigation of current trends to increase the number of embedded processors in SoCs, leading to the concept of "sea of processors" systems.