Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nm

TL;DR

This paper demonstrates how Virtual Silicon's Power Management IP can effectively reduce both dynamic and static power in 130 nm SoC designs by creating independent voltage islands and using power-saving standard cells.

Contribution

It introduces a method for implementing power islands with voltage level shifting and isolation cells, enabling significant power savings with minimal impact on performance.

Findings

Power islands can be turned off to save power.

Voltage scaling reduces power consumption at 130 nm.

Power reduction achieved with minimal area and speed impact.

Abstract

At 130 nm and 90 nm, power consumption (both dynamic and static) has become a barrier in the roadmap for SoC designs targeting battery powered, mobile applications. This paper presents the results of dynamic and static power reduction achieved implementing Tensilica's 32-bit Xtensa microprocessor core, using Virtual Silicon's Power Management IP. Independent voltage islands are created using Virtual Silicon's VIP PowerSaver standard cells by using voltage level shifting cells and voltage isolation cells to implement power islands. The VIP PowerSaver standard cells are characterized at 1.2V, 1.0V and 0.8V, to accommodate voltage scaling. Power islands can also be turned off completely. Designers can significantly lower both the dynamic power and the quiescent or leakage power of their SoC designs, with very little impact on speed or area using Virtual Silicon's VIP Gate Bias standard cells.