Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study

TL;DR

This paper presents a BIST-based testing approach for logic cores in SoC environments, leveraging P1500 standards to enhance test efficiency, fault coverage, and diagnostic capabilities while minimizing area overhead and performance impact.

Contribution

It introduces a P1500 compliant BIST methodology for logic core testing, demonstrating advantages over traditional scan-based and ATPG methods in fault coverage and test efficiency.

Findings

Achieved high fault coverage with the proposed BIST approach

Reduced area overhead compared to full scan methods

Maintained at-speed testing with minimal performance slowdown

Abstract

In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in System-on-a-chip (SoC) environments. The approach advantages are the ability to protect the core IP, the simple test interface (thanks also to the adoption of the P1500 standard), the possibility to run the test at-speed, the reduced test time, and the good diagnostic capabilities. The paper reports figures about the achieved fault coverage, the required area overhead, and the performance slowdown, and compares the figures with those for alternative approaches, such as those based on full scan and sequential ATPG.