A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18$\mu$m Digital CMOS

TL;DR

This paper presents a 12-bit pipeline ADC fabricated in 0.18μm digital CMOS technology, achieving 110MS/s with 10.4 effective bits, 97mW power, and scalable performance across a wide speed range.

Contribution

It introduces a 12-bit pipeline ADC in digital CMOS with a novel switched capacitor bias circuit for scalable power and performance.

Findings

Achieves 110MS/s sampling rate with 10.4 effective bits.

Consumes 97mW power at 110MS/s.

Supports scalable power and performance from 20 to 140MS/s.

Abstract

A 12 bit Pipeline ADC fabricated in a 0.18 $\mu$m pure digital CMOS technology is presented. Its nominal conversion rate is 110MS/s and the nominal supply voltage is 1.8V. The effective number of bits is 10.4 when a 10MHz input signal with 2V_{P-P} signal swing is applied. The occupied silicon area is 0.86mm^2 and the power consumption equals 97mW. A switched capacitor bias current circuit scale the bias current automatically with the conversion rate, which gives scaleable power consumption and full performance of the ADC from 20 to 140MS/s.