Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs

TL;DR

This paper presents a comprehensive debug support, calibration, and emulation framework for complex multi-processor SoCs, enhancing development efficiency through architecture innovations like multi-core debugging, precise timing, and integrated trace buffers.

Contribution

It introduces novel debug and emulation architectures, including Multi-Core Debug Support and Package Sized-ICE, enabling flexible, cycle-accurate debugging without external hardware modifications.

Findings

Supports cross-triggering and multi-core breakpoints

Ensures cycle-level trace ordering with on-chip timestamping

Provides integrated debug resources without external emulation boxes

Abstract

The introduction of complex SoCs with multiple processor cores presents new development challenges, such that development support is now a decisive factor when choosing a System-on-Chip (SoC). The presented developments support strategy addresses the challenges using both architecture and technology approaches. The Multi-Core Debug Support (MCDS) architecture provides flexible triggering using cross triggers and a multiple core break and suspend switch. Temporal trace ordering is guaranteed down to cycle level by on-chip time stamping. The Package Sized-ICE (PSI) approach is a novel method of including trace buffers, overlay memories, processing resources and communication interfaces without changing device behavior. PSI requires no external emulation box, as the debug host interfaces directly with the SoC using a standard interface.